Semiconductor-on-insulator (SOI) technology was first commercialized in the late 1990s. The defining characteristic of SOI technology is that the semiconductor region in which circuitry is formed is isolated from bulk substrate by an electrically insulating layer. This insulating layer is typically silicon-dioxide. The reason silicon-dioxide is chosen is that it can be formed on a wafer of silicon by oxidizing the wafer and is therefore amenable to efficient manufacturing. The advantageous aspects of SOI technology stem directly from the ability of the insulator layer to electronically isolate the active layer from bulk substrate. As used herein and in the appended claims, the region in which signal-processing circuitry is formed on an SOI structure is referred to as the active layer of the SOI structure. The term “active layer” is also used herein, and in the appended claims, to refer to any region of circuitry formed on any substrate. For example, an active layer may contain both active and passive devices. Moreover, the circuitry referred to by the term “active layer” need not contain any active devices; rather, such a layer may contain only passive devices. Examples of such passive circuits include bandpass filters and resistor dividers.
SOI technology represents an improvement over traditional bulk substrate technology because the introduction of the insulating layer isolates the active devices in an SOI structure which improves their electrical characteristics. For example, the threshold voltage of a transistor is desirously uniform, and is set in large part by the characteristics of the semiconductor material underneath the transistor's gate. If this region of material is isolated, there is less of a chance that further processing will affect this region and alter the threshold voltage of the device. Additional electrical characteristic improvements stemming from the use of the SOI structure include fewer short channel effects, decreased capacitance for higher speed, and lower insertion loss if the device is acting as a switch. In addition, the insulating layer can act to shield the active devices from harmful radiation. This is particularly important for integrated circuits that are used in space given the prevalence of harmful ionizing radiation outside the earth's atmosphere.
SOI wafer 100 is shown in FIG. 1. The wafer includes substrate layer 101, insulator layer 102, and active layer 103. The substrate is typically a semiconductor material such as silicon. Insulator layer 102 is a dielectric which is often silicon-dioxide formed through the oxidation of substrate layer 101. Active layer 103 includes a combination of dopants, dielectrics, polysilicon, metal layers, passivation, and other layers that are present after circuitry 104 has been formed therein. Circuitry 104 may include metal wiring; passive devices such as resistors, capacitors, and inductors; and active devices such as transistors. As used herein and in the appended claims, the “top” of SOI wafer 100 references top surface 105 while the “bottom” of SOI wafer 100 references bottom surface 106. This orientation scheme persists regardless of the relative orientation of SOI wafer 100 to other frames of reference, and the removal of layers from, or the addition of layers to SOI wafer 100. Therefore, active layer 103 is always “above” insulator layer 102. In addition, a vector originating in the center of active layer 103 and extending towards bottom surface 106 will always point in the direction of the “back side” of the SOI structure regardless of the relative orientation of SOI wafer 100 to other frames of references, and the removal of layers from, or the addition of layers to SOI wafer 100.
Semiconductor devices can be subject to a phenomenon known as the floating-body effect. Semiconductor-on-insulator devices are particularly susceptible to this effect. The manner in which the floating-body effect is exhibited by an n-type field effect transistor (NFET) will be described for illustrative purposes, but the floating-body effect is exhibited by many other active devices. FIG. 1B displays a side-view of NFET 108. NFET 108 is an SOI device, and is therefore disposed above insulator layer 102. The floating-body effect is caused by the presence of excess carriers in body 109. Carriers can build up in body 109 through random generation of electron and hole pairs by thermal or optical means, through scattering of high speed electrons in channel 110, through leakage from source 111 or drain 112, through band-to-band tunneling, or through avalanche breakdown in channel 110. The presence of excess carriers is therefore inevitable in any semiconductor device. However, in an SOI device, body 109 is isolated and limited as compared to a device whose body is part of bulk substrate. Therefore, far fewer excess carriers are needed to alter the characteristics of the active device.
Two alterations to the characteristics of an active device caused by the floating-body effect that are exacerbated by an SOI structure are the kink effect, and the non-linear capacitance exhibited by an active device that is in an off state. The introduction of excess carriers to body 109 due to avalanche breakdown caused by a high potential applied across source 111 and drain 112 will have the effect of greatly increasing the current through channel 110. The effect is called the kink effect because the relatively flat portion on a curve of the channel current against the drain-source potential will have a kink upwards at the point where this effect takes hold. The relatively flat portion of the curve is located in a region where the current is—for some applications—desirously set predominately by the voltage at gate 113. This effect can therefore be problematic because certain analog circuit applications are dependent upon the current of an active device being independent of the drain-source potential when operating in this region.
In contrast to the kink effect, the non-linearity of a device's off-state capacitances is not caused by avalanche breakdown. Instead, carriers build up through other less aggressive means as described above. If the potential of body 109 shifts to a significant enough degree, the capacitance seen by a signal at drain 112 will change in a non-linear fashion. The change will be non-linear because the excess carriers will build up in body 109 over time making the capacitance time-variant. Also, the charge build up will make the capacitance of the junction between body 109 and drain 112 dependent upon the signal at drain 112 which is also a characteristic of a non-linear system. This effect can be problematic because certain circuit designs are dependent upon the retention of a highly linear characteristic for their processed signals. For example, if NFET 108 was being used as a switch in a radio-frequency (RF) application wherein it had to be in an off state while a signal was transmitted on a line connected to drain 112, the capacitance from drain 112 to body 109 would have to be linear in order to prevent the production of unwanted harmonic distortion and inter-modulation distortion in the signal.
A common solution to the floating-body effect in SOI devices includes the introduction of a connection from body 109 to source 111. This solution is a subset of the more general family of solutions involving the use of what is called a “body tie”, or “body contact”. A body contact provides a connection to body 109 which serves to remove excess carriers. The particular solution of connecting body 109 to source 111 is employed most commonly because it is so simple. Unwanted charge that builds up in body 109 will be able to escape from body 109 to source 111, and will therefore not cause the kink effect or lead to the production of a non-linear capacitance.
Another solution to the floating-body effect in SOI devices involves the use of a smart body tie. A smart body tie is a body tie that changes its state based on the state of the device for which it is providing a tie. An example of a smart body tie can be described with reference to FIG. 1C. FIG. 1C comprises an NFET 114. The source of NFET 114 is connected to ground 115. The drain of NFET 114 is connected to drain contact 116. The gate of NFET 114 is connected to gate contact 117, and the cathode of diode 118. The body of NFET 114 is connected to the anode of diode 118. A similar configuration could function by replacing NFET 114 with a PFET and reversing the polarity of diode 118. This structure is advantageous in certain situations because the body tie formed by diode 118 will conduct much more when the device is off as compared to when the device is on. This can be very helpful for the situation described above wherein a non-linear off-state capacitance of the FET would imbue a processed signal on drain contact 116 with distortion. When gate contact 117 is low and the device is off, current will flow from the body of NFET 114 to gate contact 117 through diode 118. However, when gate contact 117 is high, the path from the body to gate will effectively be cut off. This can be highly advantageous given that the kink effect provides a benefit from the perspective of providing higher current during the device's on-state current. Therefore, this structure allows for the drawbacks of the floating body effect in one application to be eliminated while preserving the advantages of the floating body effect.
Although these approaches have advantageous aspects in that they are able to remove excess charge from the body of an active device, they are at the same time slightly problematic because they generally require another layer of processing in close contact to the active devices. This additional processing can complicate the fabrication process and can generally lead to non-idealities in the fabricated active devices through manufacturing errors. In addition, these approaches require additional area on the active wafer which increases the cost of the overall design. These approaches also suffer from the disadvantage of high resistance along the width of the transistor from the body tie to the most remote portion of the channel. High resistance can reduce the efficacy of the body tie in reducing floating body effects. Finally, these approaches may introduce parasitic capacitance to nodes of the device that will limit the speed of any circuit utilizing such a device.
Additionally, because of their unique structure, semiconductor-on-insulator integrated circuit chips offer opportunities to fit more electronic functions into smaller packages. Integrated circuit chips are typically attached to printed circuit boards. These boards contain one or more layers of metal traces and vias, providing electrical connections to chips and other components, thus completing the electronic system. By using innovative ways of attaching their component chips, boards can be made smaller in order to fit into smaller devices.
Integrated circuit chips can be attached to printed circuit boards in several ways. Often they are mounted in packages that have various configurations of pins, which, in turn, are inserted into holes in the printed circuit boards and fixed in place. For a smaller outline, the packaging step can be omitted, and the chip can be mounted directly on the board. A common chip mounting technique—for mounting chips both in packages and directly on boards—is wire bonding. In this method, thin wires connect pads in the package, or on the board, to pads on the chip. Usually, these bonding pads lie along the outside edges of the upper surface of the chip.
Since the board area needed for a wire-bonded chip exceeds the chip area by the length of the wires, other methods are available to replace wire bonding. In a second method, known as flip-chip or C4 (for controlled collapse chip connection), bond pads on the chip are coated with solder bumps, and the chip is mounted face down on the board. In this method, the footprint on the board used by the chip is no larger than the area of the chip. Eliminating the long wires may have performance advantages as well.
Another method of reducing board size is to stack chips on top of each other, while still being electrically connected to the board. Designers often find it advantageous to stack related chips—for example, a memory chip and its controller. In this case, the upper chip is usually connected directly to lower chip, and not necessarily to the board. Such a stacked chip assembly will typically require a vertical connection, such as a through-silicon via, to route signals and/or power to at least one of the chips. Such vertical connections, though expensive, can result in substantial package size reductions, especially if this technique is combined with flip-chip mounting. In these assemblies, both chips are either upside down, with C4 bumps formed on the lower chip; or they are mounted face-to-face, with the C4 bumps formed directly on vertical connectors.
In some cases, chip stacking may be beneficial but vertical connections are not required. For example, multiple identical memory chips may be connected to one controller chip, so as to increase memory capacity. In this case, the memory chips could be stacked and bonded individually to the printed circuit board, connecting them to the nearby controller chip. In these cases, both chips are typically mounted right side up, and both are wire bonded to the board. However, some of the area savings afforded by chip stacking is lost due to the area consumed by the multitude of wire bonds.
Thus, there is an increasing need to produce small, complex circuit boards in a cost-efficient manner.